Selection Guide

Same function — so why this part and not that one

Platform comparisons, tiered configurations and common design pitfalls across six areas. Specifications are taken item by item from vendor sources with the verification date noted; where we could not confirm a figure we say so rather than infer it.

Motor Drives & Motion Control

VFDs · Servo drives · Compressors · Multi-axis platforms

System structure

What actually drives the choice

Loop rate sets the floor on compute; current loops typically start at 10–20 kHz
Torque ripple comes from sampling resolution and PWM resolution together, not clock rate alone
Power devices and drivers get swapped wholesale between power tiers, while the controller is expected to carry over
Industrial equipment lives long enough that controller availability matters more than unit price

Platform comparison

Criterion	STM32G474 (ST)	TMS320F280039C (TI)
Core	Cortex-M4F @ 170 MHz with DSP instructions	C28x 32-bit DSP @ 120 MHz
Coprocessor	None	CLA @ 120 MHz, IEEE 754 single-precision FP
Math acceleration	CORDIC + FMAC hardware accelerators	TMU + CLA offloading loop math
ADC	3–5 × 12-bit @ 4 MSPS, 16-bit hardware oversampling	3 × 12-bit @ 4 MSPS, up to 23 external channels
High-resolution PWM	HRTIM 184 ps (G4x4 lines only)	16 ePWM channels, 8 with 150 ps HRPWM
Comparators	3–7 ultra-fast comparators	4 × CMPSS windowed comparators with 12-bit reference DAC
DAC	4–7 channels	2 × 12-bit buffered outputs
Encoder interface	Timer encoder mode	2 × dedicated eQEP modules
Communications	Up to 3 × FDCAN	CAN-FD, FSI 200 Mbps, PMBus
Flash / RAM	32–512 KB / up to 128 KB incl. CCM-SRAM	384 KB across three banks / 69 KB, both ECC-protected
Programmable logic	None	CLB, 4 tiles for custom timing logic

Configuration by tier

Tier	Typical case	Controller	Power stage & drive	Current sensing
Cost-first	Single-axis VFD, fans and pumps	STM32G431 or equivalent M4F	IGBT module + integrated half-bridge driver	Single-shunt sensing straight into the on-chip ADC
Balanced	General servo, multi-axis platforms	STM32G474 (with HRTIM) or F280039C	IGBT or discrete MOSFET + isolated gate drive	Dual-shunt or fluxgate current sensing
High-dynamic	High-speed servo, precision force control	Higher-end C2000 (CLA + CLB)	SiC MOSFET + high-speed isolated drive	SDFM / Σ-Δ isolated sensing

Where designs go wrong

HRTIM is not across the whole family

The 184 ps high-resolution timer exists only on STM32G4x4 lines. Selecting at family level and discovering at prototype stage that the part in hand has no HRTIM is a common cause of rework.

Channel count runs out before sample rate does

On multi-axis or multi-rail designs the constraint is usually channel count, not throughput, and the fix is an external ADC. Count the sampling points before choosing.

What emulating an encoder interface costs

Timer encoder mode works without a dedicated QEP block, but edge handling and error detection at speed fall to software and consume interrupt budget. The gap widens on multi-axis systems.

Do not change the controller when the power tier changes

Moving from IGBT to SiC while also changing controller platform doubles the firmware and certification work. Leaving PWM resolution headroom up front is far cheaper than switching later.

Sources

Specifications taken from the ST STM32G4 series page and the TI TMS320F280039C product page, verified 2026-09. Per-device differences follow the latest datasheets.

Digital Power & Energy Conversion

Storage PCS · EV charging · Server PSU · PV inverters

System structure

What actually drives the choice

Loop bandwidth is limited by total sample-compute-update latency, not by clock rate
PWM resolution sets the duty step, which sets the smallest achievable output adjustment
Efficiency, power density and device cost squeeze each other; fix the tier before picking parts
Long-term availability of the power devices usually affects the program more than datasheet efficiency deltas

Platform comparison

Criterion	STM32G474 (ST)	TMS320F280039C (TI)	TMS320F28P551SG (TI)
Core	Cortex-M4F @ 170 MHz	C28x @ 120 MHz	C28x @ 160 MHz
Loop coprocessor	None (CORDIC / FMAC acceleration)	CLA @ 120 MHz, single-precision FP	CLA, executing in parallel with the main core
PWM resolution	HRTIM 184 ps (G4x4 only)	HRPWM 150 ps on 8 channels	HRPWM; channel count per datasheet
ADC	3–5 × 12-bit @ 4 MSPS	3 × 12-bit @ 4 MSPS	5 ADCs
Isolated sensing interface	External solution required	External solution required	Integrated SDFM, connects directly to Σ-Δ modulators
Fast protection	3–7 ultra-fast comparators	4 × CMPSS with 12-bit reference	CMPSS + PWM trip
Custom logic	None	CLB, 4 tiles	CLB
Security	Line-dependent	—	Integrated AES
Flash	32–512 KB	384 KB across three banks, ECC-protected	512 KB
Board-to-board	FDCAN	FSI 200 Mbps + CAN-FD	CAN-FD and others, per datasheet

Configuration by tier

Tier	Typical case	Controller	Power devices	Isolation & sensing
Cost-first	Low/mid-power DC-DC, auxiliary supplies, small charging modules	STM32G431 / G474	Si MOSFET or IGBT	Opto isolation + on-chip ADC
Balanced	Charging modules, single-unit storage converters	F280039C or G474 (HRTIM)	Discrete SiC MOSFET	Digital isolators + isolated amplifiers
High power density	High-power PCS, high-efficiency server PSU	F28P551SG (SDFM) or higher-end C2000	SiC modules + high-speed isolated drive	Σ-Δ modulators direct to SDFM

Where designs go wrong

FSI gets overlooked and it matters

In paralleled or master-slave architectures, forcing board-to-board sync onto ordinary SPI leaves little noise immunity or timing margin. C2000 FSI (200 Mbps) exists for exactly this; decide whether you need it during selection.

SDFM decides the isolated-sensing cost structure

A device with SDFM connects straight to Σ-Δ modulators, removing the isolated-amp-plus-ADC combination. Without it you rebuild that externally, changing both BOM and board area. Settle this early.

ECC is not functional safety

ECC on Flash and RAM is a reliability feature, not evidence of a functional-safety grade. If the program targets SIL or an ISO standard, select against the certification requirement rather than inferring from ECC.

SiC pays off only at system level

SiC costs more per device, and the efficiency gain only closes when counted against thermals, magnetics volume and rack density. At low power tiers it often does not pay back — decide during selection, not after prototyping.

Sources

Specifications from the ST STM32G4 series page, the TI TMS320F280039C product page and the C2000 portfolio page, verified 2026-09. Some F28P551SG details follow the latest datasheet.

Industrial Networking & Edge Gateways

Remote I/O · Protocol gateways · Line data capture · PLC expansion

System structure

What actually drives the choice

Start from the protocol stack, not the processor; concurrent multi-protocol is a different problem from single-protocol conversion
Whether real-time tasks must run outside Linux decides if you need a Cortex-M coprocessor
Port count and whether you need switching usually bind before CPU frequency does
Industrial temperature range and longevity requirements eliminate a whole class of consumer-grade options

Platform comparison

Criterion	STM32MP135 (ST)	STM32MP133 (ST)	STM32MP157 (ST)
Application processor	Single-core Cortex-A7 @ 1 GHz	Single-core Cortex-A7 @ 1 GHz	Dual-core Cortex-A7 @ 800 MHz
Real-time coprocessor	None	None	Cortex-M4 @ 209 MHz
GPU	None	None	3D GPU
Ethernet	Single port	Dual port	Line-dependent
CAN FD	Per selection table	Supported	From MP153 upward
Display interface	Parallel LCD	—	MIPI-DSI
Camera interface	Supported	—	Supported
Typical positioning	Capture terminal with a local display	Dual-port protocol gateway	Cases needing Linux plus a real-time domain

Configuration by tier

Tier	Typical case	Processor	Network & fieldbus	Storage & support
Light capture	Single-protocol conversion, remote I/O expansion	STM32MP131 / MP135	Single Ethernet + RS-485	NAND / eMMC + isolated supplies
Dual-port gateway	Fieldbus to industrial Ethernet bridging	STM32MP133	Dual Ethernet + CAN FD	eMMC + redundant supply
Edge processing	Local pre-processing, gateway with HMI	STM32MP157 (A7 + M4)	Ethernet + multiple buses	eMMC + DDR3L + display

Where designs go wrong

Heterogeneous cores are not free

An A7 + M4 pairing lifts real-time work out of Linux, but inter-core messaging, memory partitioning and boot order all need designing. Where determinism requirements are mild, the extra core buys complexity and cost.

Two ports is not a switch

Two MACs and a layer-2 switch are different things. Ring or daisy-chain topologies usually need an external switch device or a part with switching built in. Confirming this during selection is cheaper than fixing it after layout.

TSN has to be confirmed separately

If a program requires TSN, it cannot be inferred from the phrase "industrial Ethernet"; device and stack support must be checked item by item. ST does not state TSN support for STM32MP1 on its product page, so this table makes no claim.

Industrial temperature changes the candidate set

A −40 °C to 85 °C-plus requirement filters processors, memory die and crystals at the same time. Memory and crystals are the ones most often missed, and they surface at thermal test.

Sources

Specifications from the ST STM32MP1 series page, verified 2026-09. TSN support is not stated by the vendor, so no claim is made here. Per-line interface differences follow the selection tables and datasheets.

FPGA Signal Processing & I/O Expansion

High-speed acquisition · Protocol bridging · I/O fan-out · Image pre-processing

System structure

What actually drives the choice

First decide whether an FPGA is actually needed; running out of interfaces and running out of compute have different answers
Size logic on worst case; timing closure degrades sharply once utilisation passes roughly 70–80%
Whether you need a hard ARM core is the watershed; it changes architecture, software stack and team split
Toolchain versioning and IP licensing are hidden costs that usually surface mid-program

Platform comparison

Criterion	Artix-7 (AMD)	Zynq-7000 SoC (AMD)
Device type	Programmable logic only	SoC: hard processor plus programmable logic
Hard processor	None (soft core optional)	Arm Cortex-A9 processing system
Logic capacity range	Roughly 13,000 – 200,000 logic cells across the family	Varies by device, spanning small to mid-large capacity
Common device capacity	XC7A35T ≈ 33,280 LC; XC7A100T ≈ 101,440 LC	Per device selection table
DSP resources	XC7A35T: 90 DSP slices; XC7A100T: 240	Per device selection table
Transceivers	Up to 6.6 Gb/s	On selected devices; confirm per part
Where it fits	Parallel processing, timing-critical tasks, I/O fan-out	Systems pairing Linux or a complex stack with custom logic
Team requirement	Primarily RTL and timing-closure skills	Needs embedded software and logic design together

Configuration by tier

Tier	Typical case	Device direction	Typical interfaces	Support considerations
I/O expansion	MCU pin or port count exhausted, fan-out needed	Small-capacity FPGA / CPLD, including low-power Lattice families	LVDS, parallel bus, multiple UARTs	Focus on power sequencing and I/O bank voltage domains
Parallel processing	High-speed acquisition, real-time filtering, protocol bridging	Mid-capacity Artix-7	High-speed ADC interfaces, transceiver links	Multi-rail power and clock tree need planning up front
Software-logic co-design	Linux required alongside custom logic	Zynq-7000 SoC	Ethernet, DDR, custom peripherals	DDR routing and boot media are the usual risk points

Where designs go wrong

Identify whether the bottleneck is I/O or compute

If the shortage is interfaces, a small CPLD or an expander is often enough; only genuine parallel-compute needs justify an FPGA. Getting this wrong changes cost and schedule by an order of magnitude.

Size backwards from about 70% utilisation

A device that only just fits leaves no room to iterate, and congestion makes timing closure painful. Dividing target utilisation by roughly 0.7 when sizing is cheaper than moving to a bigger device later.

Toolchain and IP licences are hidden costs

Toolchain version, whether a paid licence is required, and whether the IP cores you plan to use are free all affect real development cost. Settle this during selection, not mid-development.

A hard ARM core changes the team, not just the chip

Moving from a pure FPGA to a SoC like Zynq is not only a device change; it requires embedded Linux and logic design capability at once. If the team has only one side, budget for outside help as part of the solution.

Sources

The Artix-7 family capacity range (roughly 13,000–200,000 logic cells) and the 6.6 Gb/s transceiver rate come from the AMD Artix-7 product brief, verified 2026-09. Logic cell and DSP slice counts for XC7A35T / XC7A100T come from the 7-series selection guide; AMD product pages timed out repeatedly during verification, so parameters we could not confirm item by item — Block RAM among them — are deliberately omitted here. Refer to DS180 / DS181. Zynq-7000 and Lattice entries are architectural descriptions; per-device figures need separate confirmation.

Precision Signal Chain & Data Acquisition

Test & measurement · Sensor front-ends · Weighing · Process control

System structure

What actually drives the choice

Real accuracy comes from the noise floor of the whole chain, not the bit count on the ADC datasheet
Fix signal bandwidth and channel-switching behaviour before choosing between Σ-Δ and SAR
Reference drift is often the real limit on long-term accuracy, and the most commonly overlooked part
Isolation requirements change supply, interface and layout together, so decide early

Platform comparison

Criterion	Σ-Δ 架构（以 AD7124-8 为例）	SAR 架构
Typical resolution	AD7124-8: 24-bit	Commonly 12–18 bit
Output data rate	Full power: 9.38 SPS – 19.2 kSPS	Hundreds of kSPS to several MSPS
Noise performance	About 24 nV rms at 1.17 SPS, gain 128, low-power mode	Depends on device and front-end design
Noise-free bits	Up to 22 noise-free bits at gain 1 across power modes	Per device specification
Channel capability	8 differential or 15 pseudo-differential	Usually multiplexed, with settling time after switching
Integrated gain	PGA, gain 1–128	Typically needs an external instrumentation amp
Integrated reference	Band-gap reference, max 10 ppm/°C drift	Usually external
Excitation	Matched programmable excitation currents, suited to RTD and bridge sensing	External
Supply	2.7–3.6 V single, or ±1.8 V dual	Per device specification
Where it fits	Temperature, pressure and weighing: low bandwidth, high accuracy	Fast per-channel sampling or higher bandwidth

Configuration by tier

Tier	Typical case	ADC direction	Front-end	Reference & supply
Low-speed, high-accuracy	RTD temperature, weighing, bridge sensing	Σ-Δ with integrated PGA and excitation, e.g. AD7124-8	External instrumentation amp often unnecessary	Use the internal reference, watch the drift spec
Mid-speed, multi-channel	Multi-channel process monitoring, condition monitoring	Σ-Δ or mid-speed SAR, depending on switching needs	Instrumentation amp plus anti-alias filtering	External low-noise reference and low-noise LDO
High-bandwidth	Vibration analysis, power quality, transient capture	High-speed SAR or simultaneous-sampling ADC	Driver amplifier and settling time designed together	Supply noise lands in the result; partition the supplies

Where designs go wrong

Bits are not accuracy

A 24-bit device may deliver only low-twenties noise-free bits at your actual gain and rate. Select on the noise figure at the intended operating point, not on nominal resolution.

Reference drift sets long-term accuracy

Passing calibration at room temperature says little about field behaviour. Across industrial temperature, reference drift in ppm/°C often dominates the error budget before the ADC does. Budget for it during selection.

Settling time after channel switching

In multiplexed acquisition each channel change needs settling before the reading is valid. Estimating throughput as channels times per-channel rate is usually optimistic and does not survive measurement.

Decide isolation early

Whether to isolate changes supply architecture, interface choice and layout partitioning at once. Adding isolation at prototype stage usually means redesigning supplies and ground planes, not adding a part.

Sources

AD7124-8 figures come from the ADI product page, verified 2026-09. The SAR column describes architectural characteristics rather than a specific device; confirm against the datasheet of whichever part is chosen.

Edge AI Hardware Platforms

Machine vision · Inference boxes · Smart cameras · Inspection systems

System structure

What actually drives the choice

Fix the model and frame rate before discussing compute; a TOPS number detached from a model is not comparable
Imaging bandwidth and ISP capability usually bind before inference throughput does
Power-tree and sequencing complexity scales with compute, and is the main failure mode on these boards
Thermal headroom must be sized on sustained load, not on the nominal power quoted with peak compute

Platform comparison

Criterion	AM62A7 (TI)	STM32MP2 系列 (ST)
Application cores	Quad-core Cortex-A53 up to 1.4 GHz	Single or dual Cortex-A35 up to 1.5 GHz
Real-time / secure core	Two single-core Cortex-R5F @ 800 MHz	Cortex-M33 up to 400 MHz, can serve as trusted boot domain
AI acceleration	C7x deep-learning accelerator, up to 2 TOPS (8-bit) at 1.0 GHz	NPU on MP25x / MP23x; vendor page states no TOPS figure
Floating-point	40 GFLOPS	Not stated on the vendor page
ISP	315 MPixel/s, 5 MP @ 60 fps, max line width 4096 px	Line-dependent; check the datasheet
Camera interface	MIPI CSI-2 v1.3, 4-lane D-PHY	Line-dependent
Display	DPI 24-bit RGB, up to 2048×1080 @ 60 fps	GPU up to 900 MHz on MP25x
Ethernet	Three-port gigabit switch (two external), with TSN support	1–3 ports depending on line; TSN not stated
Fieldbus	Confirm per device	1–3 × FD-CAN
Temperature range	−40 °C to 125 °C	−40 °C to 125 °C

Configuration by tier

Tier	Typical case	Compute direction	Imaging path	Power & storage
Light inference	Fixed-station classification, code reading, presence checks	MPU with NPU, in the STM32MP23x / MP25x direction	Single MIPI camera at moderate resolution	Simpler power tree; watch boot order for the M33 domain
Vision inspection	Line defect detection, multi-object tracking	AM62A7 (2 TOPS with dedicated ISP)	High-frame-rate MIPI input with ISP pre-processing	Multi-rail supply with sequencing device, eMMC as baseline
Multi-stream	Multi-camera aggregation, edge inference boxes	Assess whether this exceeds a single MPU	Compute the bandwidth first; it usually binds before compute	Thermals and sustained power are the binding constraints

Where designs go wrong

TOPS does not compare across platforms

Vendors define TOPS differently, quote it at different precisions, and real models rarely saturate the number. Compare measured results for the same model at the same frame rate, not nameplate figures.

Bandwidth binds before compute

When aggregating several high-resolution cameras, MIPI lanes, ISP throughput and memory bandwidth run out first. Budget that path before choosing the compute device.

Sequencing is where these boards fail

Compute platforms need many rails in a strict order. A power tree assembled ad hoc from discrete DC-DCs tends to produce random boot failures at volume. Follow the vendor-recommended PMIC or sequencing approach.

Size thermals on sustained load

Inference workloads sit near full load continuously rather than peaking occasionally. Designing thermals to nominal power invites throttling in summer or in sealed enclosures, which shows up as unchanged accuracy but falling frame rate.

Sources

AM62A7 figures come from the TI product page and STM32MP2 figures from the ST series page, both verified 2026-09. ST does not publish a TOPS figure for the NPU, so this table records that rather than inferring one. Per-device differences follow the datasheets.

Which tier is your project in?

The tiers above are a general starting point. Certification scope, enclosure space and volume all move the conclusion. Send us the constraints and we will come back within 48 hours with a view specific to your case.

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